(1) Field of the Invention
This invention relates generally to integrated circuits requiring accurate capacitance values. Specifically, the present invention introduces a method to use MOS devices as stable capacitors and comprises a method and circuits used for compensating capacitance variances of said MOS capacitors in integrated circuits in applications as oscillators, frequency references and capacitance references and a method to build capacitance references in integrated circuits.
(2) Description of the Prior Art
The capacitance of available capacitors in integrated circuits is varying more than 10% to 25%. Due to said variance of the capacitance applications requiring an accurate value of capacitance, as e.g. a suitable frequency reference cannot be implemented efficiently in integrated circuits. Therefore in integrated circuits said problems are solved in prior art by trimming e.g. an oscillator using fuses which is expensive and consuming tester time.
Typical applications where accurate values of capacitance are required are e.g. oscillators. Oscillators are circuits for convening dc power into a periodic wave-form or signal. Conventional RC oscillators advantageously furnish a low-cost timing source and allow for generation of variable frequencies by changing the resistance R, or capacitance C. Furthermore, conventional RC oscillators avoid advantageously the use of inductors, which are difficult to fabricate in integrated circuits.
Normally an RC relaxation oscillator needs a precision resistor R and also a precision capacitor C to achieve an accurate time constant T=R×C. Since both devices vary by 10–25% in integrated circuit fabrication an expensive trimming scheme or external components must be used for such a frequency reference. FIG. 1 prior art shows as example the principle of such a relaxation oscillator. Said RC oscillator comprises the current source 1 with a current       Iref    =                  U        ⁢                                  ⁢        r            R        ,a periodical switch 2, a capacitor 3 having the capacitance C, a comparator 4 having as input the voltage Uc 21 at the capacitor C 3 and the threshold voltage Uth 4 and as output the voltage Us 5. Said threshold voltage is proportional to the reference voltage Ur.Uth=k×UrThe principle is to charge a capacitor with a current Iref proportional to said reference voltage Ur. If the resulting voltage at the capacitor C 3 exceeds said threshold voltage Uth 4 a pulse or digital signal is created at the circuit output Us 5. Afterwards said capacitor C 3 is discharged/charged with the same current in order to initiate another switching event after a certain time which is defined by the switch 2. This is repeated continuously and periodically and therefore creates a constant frequency at the circuit output Us 5. FIG. 2 prior art shows the voltage Uc 21 at the capacitor C3 (shown in FIG. 1 prior art) and FIG. 3 prior art shows the voltage at the circuit output Us 5.
The frequency f of said oscillator follows the formula   f  =            Iref              2        ×        k        ×        U        ⁢                                  ⁢        r        ×        C              =          1              2        ×        k        ×        C        ×        R            It is obvious that the accuracy of the values of the resistor R and the capacity C have a direct impact to the frequency of said oscillator. Variations in the order of magnitude of 25% are not acceptable for most applications.
U.S. Patent (U.S. Pat. No. 6,020,792 to Nolan et al.) describes a precision relaxation oscillator with temperature compensation. The precision relaxation oscillator is comprised of an oscillation generator comprised of a set-reset flip-flop and other components, a first current generator for producing a first output current and a second current generator for producing a second output current. The invention is implemented on a single, monolithic integrated circuit.
U.S. Patent (U.S. Pat. No. 5,801,411 to Klughart) discloses an integrated capacitor structure having substantially reduced temperature and voltage coefficients including a combination of conventional N-depletion and P-depletion MOS gate capacitors connected in parallel and optimized for use at low bias voltages, where both the N-depletion and P-depletion capacitor structures have substantially zero temperature coefficients in their fully depleted region of operation.
U.S. Patent (U.S. Pat. No. 5,585,765 to O'Shaughnessy) shows a low power RC oscillator including a low power bias circuit and an RC network. The RC network is used to form a time constant equal to the RC product. The RC oscillator includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.
W. M. Sansen et al. (IEEE Journal of Solid State Circuits, Vol. 23, No.3, June 1988) describe a temperature-compensated current reference for CMOS integrated circuits, based upon a MOSFET as current defining element. So as to minimize the mass production cost, it uses no external components nor trimming procedures. Comparison with classical current reference with a resistor as a current defining element shows a considerable improvement of the relative tolerances of the current.